Constant RV_Zvbc 

pub const RV_Zvbc: &str = "set = \"RVZvbc\" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b\nwidth = 32\n\n[formats]\nnames = [\"format-1-0\", \"format-2-0\"]\nparts = [\n    [\n        \"vm\",\n        1,\n        \"Mapping_vm\",\n    ],\n    [\n        \"vs2\",\n        5,\n        \"Register_vec\",\n    ],\n    [\n        \"vs1\",\n        5,\n        \"Register_vec\",\n    ],\n    [\n        \"vd\",\n        5,\n        \"Register_vec\",\n    ],\n    [\n        \"rs1_Register_int\",\n        5,\n        \"Register_int\",\n    ],\n    [\n        \"rs1_Register_float\",\n        5,\n        \"Register_float\",\n    ],\n    [\n        \"none\",\n        32,\n        \"u32\",\n    ],\n    [\n        \"imm\",\n        32,\n        \"VInt\",\n    ],\n    [\n        \"himm\",\n        32,\n        \"VInt\",\n        \"hex\",\n    ],\n]\n\n[types]\nnames = [\"type-1-0\", \"type-2-0\"]\n[[types.type-1-0]]\nname = \"none\"\ntop = 31\nbot = 26\n\n[[types.type-1-0]]\nname = \"vm\"\ntop = 0\nbot = 0\n\n[[types.type-1-0]]\nname = \"vs2\"\ntop = 4\nbot = 0\n\n[[types.type-1-0]]\nname = \"vs1\"\ntop = 4\nbot = 0\n\n[[types.type-1-0]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type-1-0]]\nname = \"vd\"\ntop = 4\nbot = 0\n\n[[types.type-1-0]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type-2-0]]\nname = \"none\"\ntop = 31\nbot = 26\n\n[[types.type-2-0]]\nname = \"vm\"\ntop = 0\nbot = 0\n\n[[types.type-2-0]]\nname = \"vs2\"\ntop = 4\nbot = 0\n\n[[types.type-2-0]]\nname = \"rs1_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type-2-0]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type-2-0]]\nname = \"vd\"\ntop = 4\nbot = 0\n\n[[types.type-2-0]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[format-1-0]\ntype = \"type-1-0\"\n\n[format-2-0]\ntype = \"type-2-0\"\n\n[mappings]\nnames = [\"Register_int\", \"Register_float\", \"Register_vec\", \"Mapping_vm\"]\nnumber = 32\nRegister_int = [\n    \"zero\",\n    \"ra\",\n    \"sp\",\n    \"gp\",\n    \"tp\",\n    \"t0\",\n    \"t1\",\n    \"t2\",\n    \"s0\",\n    \"s1\",\n    \"a0\",\n    \"a1\",\n    \"a2\",\n    \"a3\",\n    \"a4\",\n    \"a5\",\n    \"a6\",\n    \"a7\",\n    \"s2\",\n    \"s3\",\n    \"s4\",\n    \"s5\",\n    \"s6\",\n    \"s7\",\n    \"s8\",\n    \"s9\",\n    \"s10\",\n    \"s11\",\n    \"t3\",\n    \"t4\",\n    \"t5\",\n    \"t6\",\n]\nRegister_float = [\n    \"ft0\",\n    \"ft1\",\n    \"ft2\",\n    \"ft3\",\n    \"ft4\",\n    \"ft5\",\n    \"ft6\",\n    \"ft7\",\n    \"fs0\",\n    \"fs1\",\n    \"fa0\",\n    \"fa1\",\n    \"fa2\",\n    \"fa3\",\n    \"fa4\",\n    \"fa5\",\n    \"fa6\",\n    \"fa7\",\n    \"fs2\",\n    \"fs3\",\n    \"fs4\",\n    \"fs5\",\n    \"fs6\",\n    \"fs7\",\n    \"fs8\",\n    \"fs9\",\n    \"fs10\",\n    \"fs11\",\n    \"ft8\",\n    \"ft9\",\n    \"ft10\",\n    \"ft11\",\n]\nRegister_vec = [\n    \"v0\",\n    \"v1\",\n    \"v2\",\n    \"v3\",\n    \"v4\",\n    \"v5\",\n    \"v6\",\n    \"v7\",\n    \"v8\",\n    \"v9\",\n    \"v10\",\n    \"v11\",\n    \"v12\",\n    \"v13\",\n    \"v14\",\n    \"v15\",\n    \"v16\",\n    \"v17\",\n    \"v18\",\n    \"v19\",\n    \"v20\",\n    \"v21\",\n    \"v22\",\n    \"v23\",\n    \"v24\",\n    \"v25\",\n    \"v26\",\n    \"v27\",\n    \"v28\",\n    \"v29\",\n    \"v30\",\n    \"v31\",\n]\nMapping_vm = [\", v0.t\", \"\"]\n\n[format-1-0.repr]\ndefault = \"$name$ %vd%, %vs2%, %vs1%%vm%\"\n\n[format-2-0.repr]\ndefault = \"$name$ %vd%, %vs2%, %rs1_Register_int%%vm%\"\n\n[format-1-0.instructions.\"vclmul.vv\"]\nmask = 0xfc00707f\nmatch = 0x30002057\n\n[format-1-0.instructions.\"vclmulh.vv\"]\nmask = 0xfc00707f\nmatch = 0x34002057\n\n[format-2-0.instructions.\"vclmul.vx\"]\nmask = 0xfc00707f\nmatch = 0x30006057\n\n[format-2-0.instructions.\"vclmulh.vx\"]\nmask = 0xfc00707f\nmatch = 0x34006057\n";