Constant RV64_Zcb_lower
Source pub const RV64_Zcb_lower: &str = "set = \"RV64Zcb\" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b\nwidth = 32\n\n[formats]\nnames = [\n \"format-1-0\",\n \"format-2-0\",\n \"format-3-0\",\n \"format-4-0\",\n \"format-5-0\",\n \"format-6-0\",\n]\nparts = [\n [\n \"rd_p_Register_int_c\",\n 3,\n \"Register_int_c\",\n ],\n [\n \"rd_p_Register_float_c\",\n 3,\n \"Register_float_c\",\n ],\n [\n \"rs1_p_Register_int_c\",\n 3,\n \"Register_int_c\",\n ],\n [\n \"rs1_p_Register_float_c\",\n 3,\n \"Register_float_c\",\n ],\n [\n \"rd_rs1_p_Register_int_c\",\n 3,\n \"Register_int_c\",\n ],\n [\n \"rd_rs1_p_Register_float_c\",\n 3,\n \"Register_float_c\",\n ],\n [\n \"rs2_p_Register_int_c\",\n 3,\n \"Register_int_c\",\n ],\n [\n \"rs2_p_Register_float_c\",\n 3,\n \"Register_float_c\",\n ],\n [\n \"none\",\n 32,\n \"u32\",\n ],\n [\n \"imm\",\n 32,\n \"VInt\",\n ],\n [\n \"himm\",\n 32,\n \"VInt\",\n \"hex\",\n ],\n]\n\n[types]\nnames = [\"type-1-0\", \"type-2-0\", \"type-3-0\", \"type-4-0\", \"type-5-0\", \"type-6-0\"]\n[[types.type-1-0]]\nname = \"none\"\ntop = 31\nbot = 10\n\n[[types.type-1-0]]\nname = \"rs1_p_Register_int_c\"\ntop = 2\nbot = 0\n\n[[types.type-1-0]]\nname = \"himm\"\ntop = 0\nbot = 0\n\n[[types.type-1-0]]\nname = \"himm\"\ntop = 1\nbot = 1\n\n[[types.type-1-0]]\nname = \"rd_p_Register_int_c\"\ntop = 2\nbot = 0\n\n[[types.type-1-0]]\nname = \"none\"\ntop = 1\nbot = 0\n\n[[types.type-2-0]]\nname = \"none\"\ntop = 31\nbot = 10\n\n[[types.type-2-0]]\nname = \"rs1_p_Register_int_c\"\ntop = 2\nbot = 0\n\n[[types.type-2-0]]\nname = \"none\"\ntop = 6\nbot = 6\n\n[[types.type-2-0]]\nname = \"himm\"\ntop = 1\nbot = 1\n\n[[types.type-2-0]]\nname = \"rd_p_Register_int_c\"\ntop = 2\nbot = 0\n\n[[types.type-2-0]]\nname = \"none\"\ntop = 1\nbot = 0\n\n[[types.type-3-0]]\nname = \"none\"\ntop = 31\nbot = 10\n\n[[types.type-3-0]]\nname = \"rd_rs1_p_Register_int_c\"\ntop = 2\nbot = 0\n\n[[types.type-3-0]]\nname = \"none\"\ntop = 6\nbot = 5\n\n[[types.type-3-0]]\nname = \"rs2_p_Register_int_c\"\ntop = 2\nbot = 0\n\n[[types.type-3-0]]\nname = \"none\"\ntop = 1\nbot = 0\n\n[[types.type-4-0]]\nname = \"none\"\ntop = 31\nbot = 10\n\n[[types.type-4-0]]\nname = \"rd_rs1_p_Register_int_c\"\ntop = 2\nbot = 0\n\n[[types.type-4-0]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type-5-0]]\nname = \"none\"\ntop = 31\nbot = 10\n\n[[types.type-5-0]]\nname = \"rs1_p_Register_int_c\"\ntop = 2\nbot = 0\n\n[[types.type-5-0]]\nname = \"himm\"\ntop = 0\nbot = 0\n\n[[types.type-5-0]]\nname = \"himm\"\ntop = 1\nbot = 1\n\n[[types.type-5-0]]\nname = \"rs2_p_Register_int_c\"\ntop = 2\nbot = 0\n\n[[types.type-5-0]]\nname = \"none\"\ntop = 1\nbot = 0\n\n[[types.type-6-0]]\nname = \"none\"\ntop = 31\nbot = 10\n\n[[types.type-6-0]]\nname = \"rs1_p_Register_int_c\"\ntop = 2\nbot = 0\n\n[[types.type-6-0]]\nname = \"none\"\ntop = 6\nbot = 6\n\n[[types.type-6-0]]\nname = \"himm\"\ntop = 1\nbot = 1\n\n[[types.type-6-0]]\nname = \"rs2_p_Register_int_c\"\ntop = 2\nbot = 0\n\n[[types.type-6-0]]\nname = \"none\"\ntop = 1\nbot = 0\n\n[format-1-0]\ntype = \"type-1-0\"\n\n[format-2-0]\ntype = \"type-2-0\"\n\n[format-3-0]\ntype = \"type-3-0\"\n\n[format-4-0]\ntype = \"type-4-0\"\n\n[format-5-0]\ntype = \"type-5-0\"\n\n[format-6-0]\ntype = \"type-6-0\"\n\n[mappings]\nnames = [\"Register_int_c\", \"Register_float_c\"]\nnumber = 32\nRegister_int_c = [\"s0\", \"s1\", \"a0\", \"a1\", \"a2\", \"a3\", \"a4\", \"a5\"]\nRegister_float_c = [\"fs0\", \"fs1\", \"fa0\", \"fa1\", \"fa2\", \"fa3\", \"fa4\", \"fa5\"]\n\n[format-1-0.repr]\ndefault = \"$name$ %rd_p_Register_int_c%, %himm%(%rs1_p_Register_int_c%)\"\n\n[format-2-0.repr]\ndefault = \"$name$ %rd_p_Register_int_c%, %himm%(%rs1_p_Register_int_c%)\"\n\n[format-3-0.repr]\ndefault = \"$name$ %rd_rs1_p_Register_int_c%, %rs2_p_Register_int_c%\"\n\n[format-4-0.repr]\ndefault = \"$name$ %rd_rs1_p_Register_int_c%\"\n\n[format-5-0.repr]\ndefault = \"$name$ %rs2_p_Register_int_c%, %himm%(%rs1_p_Register_int_c%)\"\n\n[format-6-0.repr]\ndefault = \"$name$ %rs2_p_Register_int_c%, %himm%(%rs1_p_Register_int_c%)\"\n\n[format-1-0.instructions.\"c.lbu\"]\nmask = 0xfc03\nmatch = 0x8000\nunsigned = true\n\n[format-2-0.instructions.\"c.lh\"]\nmask = 0xfc43\nmatch = 0x8440\nunsigned = true\n\n[format-2-0.instructions.\"c.lhu\"]\nmask = 0xfc43\nmatch = 0x8400\nunsigned = true\n\n[format-3-0.instructions.\"c.mul\"]\nmask = 0xfc63\nmatch = 0x9c41\n\n[format-4-0.instructions.\"c.not\"]\nmask = 0xfc7f\nmatch = 0x9c75\n\n[format-4-0.instructions.\"c.sext.b\"]\nmask = 0xfc7f\nmatch = 0x9c65\n\n[format-4-0.instructions.\"c.sext.h\"]\nmask = 0xfc7f\nmatch = 0x9c6d\n\n[format-4-0.instructions.\"c.zext.b\"]\nmask = 0xfc7f\nmatch = 0x9c61\n\n[format-4-0.instructions.\"c.zext.h\"]\nmask = 0xfc7f\nmatch = 0x9c69\n\n[format-4-0.instructions.\"c.zext.w\"]\nmask = 0xfc7f\nmatch = 0x9c71\n\n[format-5-0.instructions.\"c.sb\"]\nmask = 0xfc03\nmatch = 0x8800\nunsigned = true\n\n[format-6-0.instructions.\"c.sh\"]\nmask = 0xfc43\nmatch = 0x8c00\nunsigned = true\n";