Skip to main content

RV64_Zbb

Constant RV64_Zbb 

Source
pub const RV64_Zbb: &str = "set = \"RV64Zbb\" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b\nwidth = 32\n\n[formats]\nnames = [\"format_1-0\", \"format_2-0\", \"format_3-0\", \"format_4-0\"]\nparts = [\n    [\n        \"rd_Register_int\",\n        5,\n        \"Register_int\",\n    ],\n    [\n        \"rd_Register_float\",\n        5,\n        \"Register_float\",\n    ],\n    [\n        \"rs1_Register_int\",\n        5,\n        \"Register_int\",\n    ],\n    [\n        \"rs1_Register_float\",\n        5,\n        \"Register_float\",\n    ],\n    [\n        \"rs2_Register_int\",\n        5,\n        \"Register_int\",\n    ],\n    [\n        \"rs2_Register_float\",\n        5,\n        \"Register_float\",\n    ],\n    [\n        \"shamtd\",\n        6,\n        \"u8\",\n        \"hex\",\n    ],\n    [\n        \"shamtw\",\n        5,\n        \"u8\",\n        \"hex\",\n    ],\n    [\n        \"none\",\n        32,\n        \"u32\",\n    ],\n    [\n        \"imm\",\n        32,\n        \"VInt\",\n    ],\n    [\n        \"himm\",\n        32,\n        \"VInt\",\n        \"hex\",\n    ],\n]\n\n[types]\nnames = [\"type_1-0\", \"type_2-0\", \"type_3-0\", \"type_4-0\"]\n[[types.type_1-0]]\nname = \"none\"\ntop = 31\nbot = 25\n\n[[types.type_1-0]]\nname = \"rs2_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_1-0]]\nname = \"rs1_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_1-0]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type_1-0]]\nname = \"rd_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_1-0]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_2-0]]\nname = \"none\"\ntop = 31\nbot = 20\n\n[[types.type_2-0]]\nname = \"rs1_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_2-0]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type_2-0]]\nname = \"rd_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_2-0]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_3-0]]\nname = \"none\"\ntop = 31\nbot = 26\n\n[[types.type_3-0]]\nname = \"shamtd\"\ntop = 5\nbot = 0\n\n[[types.type_3-0]]\nname = \"rs1_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_3-0]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type_3-0]]\nname = \"rd_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_3-0]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_4-0]]\nname = \"none\"\ntop = 31\nbot = 25\n\n[[types.type_4-0]]\nname = \"shamtw\"\ntop = 4\nbot = 0\n\n[[types.type_4-0]]\nname = \"rs1_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_4-0]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type_4-0]]\nname = \"rd_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_4-0]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[format_1-0]\ntype = \"type_1-0\"\n\n[format_2-0]\ntype = \"type_2-0\"\n\n[format_3-0]\ntype = \"type_3-0\"\n\n[format_4-0]\ntype = \"type_4-0\"\n\n[mappings]\nnames = [\"Register_int\", \"Register_float\"]\nnumber = 32\nRegister_int = [\n    \"zero\",\n    \"ra\",\n    \"sp\",\n    \"gp\",\n    \"tp\",\n    \"t0\",\n    \"t1\",\n    \"t2\",\n    \"s0\",\n    \"s1\",\n    \"a0\",\n    \"a1\",\n    \"a2\",\n    \"a3\",\n    \"a4\",\n    \"a5\",\n    \"a6\",\n    \"a7\",\n    \"s2\",\n    \"s3\",\n    \"s4\",\n    \"s5\",\n    \"s6\",\n    \"s7\",\n    \"s8\",\n    \"s9\",\n    \"s10\",\n    \"s11\",\n    \"t3\",\n    \"t4\",\n    \"t5\",\n    \"t6\",\n]\nRegister_float = [\n    \"ft0\",\n    \"ft1\",\n    \"ft2\",\n    \"ft3\",\n    \"ft4\",\n    \"ft5\",\n    \"ft6\",\n    \"ft7\",\n    \"fs0\",\n    \"fs1\",\n    \"fa0\",\n    \"fa1\",\n    \"fa2\",\n    \"fa3\",\n    \"fa4\",\n    \"fa5\",\n    \"fa6\",\n    \"fa7\",\n    \"fs2\",\n    \"fs3\",\n    \"fs4\",\n    \"fs5\",\n    \"fs6\",\n    \"fs7\",\n    \"fs8\",\n    \"fs9\",\n    \"fs10\",\n    \"fs11\",\n    \"ft8\",\n    \"ft9\",\n    \"ft10\",\n    \"ft11\",\n]\n\n[format_1-0.repr]\ndefault = \"$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%\"\n\n[format_2-0.repr]\ndefault = \"$name$ %rd_Register_int%, %rs1_Register_int%\"\n\n[format_3-0.repr]\ndefault = \"$name$ %rd_Register_int%, %rs1_Register_int%, %shamtd%\"\n\n[format_4-0.repr]\ndefault = \"$name$ %rd_Register_int%, %rs1_Register_int%, %shamtw%\"\n\n[format_1-0.instructions.andn]\nmask = 0xfe00707f\nmatch = 0x40007033\n\n[format_1-0.instructions.max]\nmask = 0xfe00707f\nmatch = 0xa006033\n\n[format_1-0.instructions.maxu]\nmask = 0xfe00707f\nmatch = 0xa007033\n\n[format_1-0.instructions.min]\nmask = 0xfe00707f\nmatch = 0xa004033\n\n[format_1-0.instructions.minu]\nmask = 0xfe00707f\nmatch = 0xa005033\n\n[format_1-0.instructions.orn]\nmask = 0xfe00707f\nmatch = 0x40006033\n\n[format_1-0.instructions.rol]\nmask = 0xfe00707f\nmatch = 0x60001033\n\n[format_1-0.instructions.rolw]\nmask = 0xfe00707f\nmatch = 0x6000103b\n\n[format_1-0.instructions.ror]\nmask = 0xfe00707f\nmatch = 0x60005033\n\n[format_1-0.instructions.rorw]\nmask = 0xfe00707f\nmatch = 0x6000503b\n\n[format_1-0.instructions.xnor]\nmask = 0xfe00707f\nmatch = 0x40004033\n\n[format_2-0.instructions.clz]\nmask = 0xfff0707f\nmatch = 0x60001013\n\n[format_2-0.instructions.clzw]\nmask = 0xfff0707f\nmatch = 0x6000101b\n\n[format_2-0.instructions.cpop]\nmask = 0xfff0707f\nmatch = 0x60201013\n\n[format_2-0.instructions.cpopw]\nmask = 0xfff0707f\nmatch = 0x6020101b\n\n[format_2-0.instructions.ctz]\nmask = 0xfff0707f\nmatch = 0x60101013\n\n[format_2-0.instructions.ctzw]\nmask = 0xfff0707f\nmatch = 0x6010101b\n\n[format_2-0.instructions.\"orc.b\"]\nmask = 0xfff0707f\nmatch = 0x28705013\n\n[format_2-0.instructions.rev8]\nmask = 0xfff0707f\nmatch = 0x6b805013\n\n[format_2-0.instructions.\"sext.b\"]\nmask = 0xfff0707f\nmatch = 0x60401013\n\n[format_2-0.instructions.\"sext.h\"]\nmask = 0xfff0707f\nmatch = 0x60501013\n\n[format_2-0.instructions.\"zext.h\"]\nmask = 0xfff0707f\nmatch = 0x800403b\n\n[format_3-0.instructions.rori]\nmask = 0xfc00707f\nmatch = 0x60005013\n\n[format_4-0.instructions.roriw]\nmask = 0xfe00707f\nmatch = 0x6000501b\n";