Constant RV32I 

pub const RV32I: &str = "set = \"RV32I\" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b\nwidth = 32\n\n[formats]\nnames = [\n    \"format_1-0\",\n    \"format_2-0\",\n    \"format_3-0\",\n    \"format_4-0\",\n    \"format_5-0\",\n    \"format_6-0\",\n    \"format_7-0\",\n    \"format_8-0\",\n    \"format_9-0\",\n]\nparts = [\n    [\n        \"rd_Register_int\",\n        5,\n        \"Register_int\",\n    ],\n    [\n        \"rd_Register_float\",\n        5,\n        \"Register_float\",\n    ],\n    [\n        \"rs1_Register_int\",\n        5,\n        \"Register_int\",\n    ],\n    [\n        \"rs1_Register_float\",\n        5,\n        \"Register_float\",\n    ],\n    [\n        \"rs2_Register_int\",\n        5,\n        \"Register_int\",\n    ],\n    [\n        \"rs2_Register_float\",\n        5,\n        \"Register_float\",\n    ],\n    [\n        \"fm\",\n        4,\n        \"u8\",\n    ],\n    [\n        \"pred\",\n        4,\n        \"Mapping_fence\",\n    ],\n    [\n        \"succ\",\n        4,\n        \"Mapping_fence\",\n    ],\n    [\n        \"shamtw\",\n        5,\n        \"u8\",\n    ],\n    [\n        \"none\",\n        32,\n        \"u32\",\n    ],\n    [\n        \"imm\",\n        32,\n        \"VInt\",\n    ],\n    [\n        \"himm\",\n        32,\n        \"VInt\",\n        \"hex\",\n    ],\n]\n\n[types]\nnames = [\n    \"type_1-0\",\n    \"type_2-0\",\n    \"type_3-0\",\n    \"type_4-0\",\n    \"type_5-0\",\n    \"type_6-0\",\n    \"type_7-0\",\n    \"type_8-0\",\n    \"type_9-0\",\n]\n[[types.type_1-0]]\nname = \"none\"\ntop = 31\nbot = 25\n\n[[types.type_1-0]]\nname = \"rs2_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_1-0]]\nname = \"rs1_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_1-0]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type_1-0]]\nname = \"rd_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_1-0]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_2-0]]\nname = \"imm\"\ntop = 11\nbot = 0\n\n[[types.type_2-0]]\nname = \"rs1_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_2-0]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type_2-0]]\nname = \"rd_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_2-0]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_3-0]]\nname = \"himm\"\ntop = 19\nbot = 0\n\n[[types.type_3-0]]\nname = \"rd_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_3-0]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_4-0]]\nname = \"imm\"\ntop = 12\nbot = 12\n\n[[types.type_4-0]]\nname = \"imm\"\ntop = 10\nbot = 5\n\n[[types.type_4-0]]\nname = \"rs2_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_4-0]]\nname = \"rs1_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_4-0]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type_4-0]]\nname = \"imm\"\ntop = 4\nbot = 1\n\n[[types.type_4-0]]\nname = \"imm\"\ntop = 11\nbot = 11\n\n[[types.type_4-0]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_5-0]]\nname = \"none\"\ntop = 31\nbot = 0\n\n[[types.type_6-0]]\nname = \"fm\"\ntop = 3\nbot = 0\n\n[[types.type_6-0]]\nname = \"pred\"\ntop = 3\nbot = 0\n\n[[types.type_6-0]]\nname = \"succ\"\ntop = 3\nbot = 0\n\n[[types.type_6-0]]\nname = \"rs1_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_6-0]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type_6-0]]\nname = \"rd_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_6-0]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_7-0]]\nname = \"imm\"\ntop = 20\nbot = 20\n\n[[types.type_7-0]]\nname = \"imm\"\ntop = 10\nbot = 1\n\n[[types.type_7-0]]\nname = \"imm\"\ntop = 11\nbot = 11\n\n[[types.type_7-0]]\nname = \"imm\"\ntop = 19\nbot = 12\n\n[[types.type_7-0]]\nname = \"rd_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_7-0]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_8-0]]\nname = \"imm\"\ntop = 11\nbot = 5\n\n[[types.type_8-0]]\nname = \"rs2_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_8-0]]\nname = \"rs1_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_8-0]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type_8-0]]\nname = \"imm\"\ntop = 4\nbot = 0\n\n[[types.type_8-0]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_9-0]]\nname = \"none\"\ntop = 31\nbot = 25\n\n[[types.type_9-0]]\nname = \"shamtw\"\ntop = 4\nbot = 0\n\n[[types.type_9-0]]\nname = \"rs1_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_9-0]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type_9-0]]\nname = \"rd_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_9-0]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[format_1-0]\ntype = \"type_1-0\"\n\n[format_2-0]\ntype = \"type_2-0\"\n\n[format_3-0]\ntype = \"type_3-0\"\n\n[format_4-0]\ntype = \"type_4-0\"\n\n[format_5-0]\ntype = \"type_5-0\"\n\n[format_6-0]\ntype = \"type_6-0\"\n\n[format_7-0]\ntype = \"type_7-0\"\n\n[format_8-0]\ntype = \"type_8-0\"\n\n[format_9-0]\ntype = \"type_9-0\"\n\n[mappings]\nnames = [\"Register_int\", \"Register_float\", \"Mapping_fence\"]\nnumber = 32\nRegister_int = [\n    \"zero\",\n    \"ra\",\n    \"sp\",\n    \"gp\",\n    \"tp\",\n    \"t0\",\n    \"t1\",\n    \"t2\",\n    \"s0\",\n    \"s1\",\n    \"a0\",\n    \"a1\",\n    \"a2\",\n    \"a3\",\n    \"a4\",\n    \"a5\",\n    \"a6\",\n    \"a7\",\n    \"s2\",\n    \"s3\",\n    \"s4\",\n    \"s5\",\n    \"s6\",\n    \"s7\",\n    \"s8\",\n    \"s9\",\n    \"s10\",\n    \"s11\",\n    \"t3\",\n    \"t4\",\n    \"t5\",\n    \"t6\",\n]\nRegister_float = [\n    \"ft0\",\n    \"ft1\",\n    \"ft2\",\n    \"ft3\",\n    \"ft4\",\n    \"ft5\",\n    \"ft6\",\n    \"ft7\",\n    \"fs0\",\n    \"fs1\",\n    \"fa0\",\n    \"fa1\",\n    \"fa2\",\n    \"fa3\",\n    \"fa4\",\n    \"fa5\",\n    \"fa6\",\n    \"fa7\",\n    \"fs2\",\n    \"fs3\",\n    \"fs4\",\n    \"fs5\",\n    \"fs6\",\n    \"fs7\",\n    \"fs8\",\n    \"fs9\",\n    \"fs10\",\n    \"fs11\",\n    \"ft8\",\n    \"ft9\",\n    \"ft10\",\n    \"ft11\",\n]\nMapping_fence = [\n    \"unknown\",\n    \"w\",\n    \"r\",\n    \"rw\",\n    \"o\",\n    \"ow\",\n    \"or\",\n    \"orw\",\n    \"i\",\n    \"iw\",\n    \"ir\",\n    \"irw\",\n    \"io\",\n    \"iow\",\n    \"ior\",\n    \"iorw\",\n]\n\n[format_1-0.repr]\ndefault = \"$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%\"\n\n[format_2-0.repr]\ndefault = \"$name$ %rd_Register_int%, %rs1_Register_int%, %imm%\"\njalr = \"$name$ %rd_Register_int%, %imm%(%rs1_Register_int%)\"\nlb = \"$name$ %rd_Register_int%, %imm%(%rs1_Register_int%)\"\nlbu = \"$name$ %rd_Register_int%, %imm%(%rs1_Register_int%)\"\nlh = \"$name$ %rd_Register_int%, %imm%(%rs1_Register_int%)\"\nlhu = \"$name$ %rd_Register_int%, %imm%(%rs1_Register_int%)\"\nlw = \"$name$ %rd_Register_int%, %imm%(%rs1_Register_int%)\"\n\n[format_3-0.repr]\ndefault = \"$name$ %rd_Register_int%, %himm%\"\n\n[format_4-0.repr]\ndefault = \"$name$ %rs1_Register_int%, %rs2_Register_int%, %imm%\"\n\n[format_5-0.repr]\ndefault = \"$name$\"\n\n[format_6-0.repr]\ndefault = \"$name$ %pred%, %succ%\"\n\n[format_7-0.repr]\ndefault = \"$name$ %rd_Register_int%, %imm%\"\n\n[format_8-0.repr]\ndefault = \"$name$ %rs2_Register_int%, %imm%(%rs1_Register_int%)\"\n\n[format_9-0.repr]\ndefault = \"$name$ %rd_Register_int%, %rs1_Register_int%, %shamtw%\"\n\n[format_1-0.instructions.add]\nmask = 0xfe00707f\nmatch = 0x33\n\n[format_1-0.instructions.and]\nmask = 0xfe00707f\nmatch = 0x7033\n\n[format_1-0.instructions.or]\nmask = 0xfe00707f\nmatch = 0x6033\n\n[format_1-0.instructions.sll]\nmask = 0xfe00707f\nmatch = 0x1033\n\n[format_1-0.instructions.slt]\nmask = 0xfe00707f\nmatch = 0x2033\n\n[format_1-0.instructions.sltu]\nmask = 0xfe00707f\nmatch = 0x3033\n\n[format_1-0.instructions.sra]\nmask = 0xfe00707f\nmatch = 0x40005033\n\n[format_1-0.instructions.srl]\nmask = 0xfe00707f\nmatch = 0x5033\n\n[format_1-0.instructions.sub]\nmask = 0xfe00707f\nmatch = 0x40000033\n\n[format_1-0.instructions.xor]\nmask = 0xfe00707f\nmatch = 0x4033\n\n[format_2-0.instructions.addi]\nmask = 0x707f\nmatch = 0x13\n\n[format_2-0.instructions.andi]\nmask = 0x707f\nmatch = 0x7013\n\n[format_2-0.instructions.jalr]\nmask = 0x707f\nmatch = 0x67\n\n[format_2-0.instructions.lb]\nmask = 0x707f\nmatch = 0x3\n\n[format_2-0.instructions.lbu]\nmask = 0x707f\nmatch = 0x4003\n\n[format_2-0.instructions.lh]\nmask = 0x707f\nmatch = 0x1003\n\n[format_2-0.instructions.lhu]\nmask = 0x707f\nmatch = 0x5003\n\n[format_2-0.instructions.lw]\nmask = 0x707f\nmatch = 0x2003\n\n[format_2-0.instructions.ori]\nmask = 0x707f\nmatch = 0x6013\n\n[format_2-0.instructions.slti]\nmask = 0x707f\nmatch = 0x2013\n\n[format_2-0.instructions.sltiu]\nmask = 0x707f\nmatch = 0x3013\n\n[format_2-0.instructions.xori]\nmask = 0x707f\nmatch = 0x4013\n\n[format_3-0.instructions.auipc]\nmask = 0x7f\nmatch = 0x17\nunsigned = true\n\n[format_3-0.instructions.lui]\nmask = 0x7f\nmatch = 0x37\nunsigned = true\n\n[format_4-0.instructions.beq]\nmask = 0x707f\nmatch = 0x63\n\n[format_4-0.instructions.bge]\nmask = 0x707f\nmatch = 0x5063\n\n[format_4-0.instructions.bgeu]\nmask = 0x707f\nmatch = 0x7063\n\n[format_4-0.instructions.blt]\nmask = 0x707f\nmatch = 0x4063\n\n[format_4-0.instructions.bltu]\nmask = 0x707f\nmatch = 0x6063\n\n[format_4-0.instructions.bne]\nmask = 0x707f\nmatch = 0x1063\n\n[format_5-0.instructions.ebreak]\nmask = 0xffffffff\nmatch = 0x100073\n\n[format_5-0.instructions.ecall]\nmask = 0xffffffff\nmatch = 0x73\n\n[format_6-0.instructions.fence]\nmask = 0x707f\nmatch = 0xf\n\n[format_7-0.instructions.jal]\nmask = 0x7f\nmatch = 0x6f\n\n[format_8-0.instructions.sb]\nmask = 0x707f\nmatch = 0x23\n\n[format_8-0.instructions.sh]\nmask = 0x707f\nmatch = 0x1023\n\n[format_8-0.instructions.sw]\nmask = 0x707f\nmatch = 0x2023\n\n[format_9-0.instructions.slli]\nmask = 0xfe00707f\nmatch = 0x1013\n\n[format_9-0.instructions.srai]\nmask = 0xfe00707f\nmatch = 0x40005013\n\n[format_9-0.instructions.srli]\nmask = 0xfe00707f\nmatch = 0x5013\n";