Constant RV32F 

pub const RV32F: &str = "set = \"RV32F\" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b\nwidth = 32\n\n[formats]\nnames = [\n    \"format_1-7\",\n    \"format_2-1\",\n    \"format_2-2\",\n    \"format_3-1\",\n    \"format_3-2\",\n    \"format_3-3\",\n    \"format_4-3\",\n    \"format_4-7\",\n    \"format_5-2\",\n    \"format_6-15\",\n    \"format_7-1\",\n]\nparts = [\n    [\n        \"rd_Register_int\",\n        5,\n        \"Register_int\",\n    ],\n    [\n        \"rd_Register_float\",\n        5,\n        \"Register_float\",\n    ],\n    [\n        \"rs1_Register_int\",\n        5,\n        \"Register_int\",\n    ],\n    [\n        \"rs1_Register_float\",\n        5,\n        \"Register_float\",\n    ],\n    [\n        \"rs2_Register_int\",\n        5,\n        \"Register_int\",\n    ],\n    [\n        \"rs2_Register_float\",\n        5,\n        \"Register_float\",\n    ],\n    [\n        \"rm\",\n        3,\n        \"Mapping_round\",\n    ],\n    [\n        \"rs3_Register_int\",\n        5,\n        \"Register_int\",\n    ],\n    [\n        \"rs3_Register_float\",\n        5,\n        \"Register_float\",\n    ],\n    [\n        \"none\",\n        32,\n        \"u32\",\n    ],\n    [\n        \"imm\",\n        32,\n        \"VInt\",\n    ],\n    [\n        \"himm\",\n        32,\n        \"VInt\",\n        \"hex\",\n    ],\n]\n\n[types]\nnames = [\n    \"type_1-7\",\n    \"type_2-1\",\n    \"type_2-2\",\n    \"type_3-1\",\n    \"type_3-2\",\n    \"type_3-3\",\n    \"type_4-3\",\n    \"type_4-7\",\n    \"type_5-2\",\n    \"type_6-15\",\n    \"type_7-1\",\n]\n[[types.type_1-7]]\nname = \"none\"\ntop = 31\nbot = 25\n\n[[types.type_1-7]]\nname = \"rs2_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_1-7]]\nname = \"rs1_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_1-7]]\nname = \"rm\"\ntop = 2\nbot = 0\n\n[[types.type_1-7]]\nname = \"rd_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_1-7]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_2-1]]\nname = \"none\"\ntop = 31\nbot = 20\n\n[[types.type_2-1]]\nname = \"rs1_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_2-1]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type_2-1]]\nname = \"rd_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_2-1]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_2-2]]\nname = \"none\"\ntop = 31\nbot = 20\n\n[[types.type_2-2]]\nname = \"rs1_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_2-2]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type_2-2]]\nname = \"rd_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_2-2]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_3-1]]\nname = \"none\"\ntop = 31\nbot = 20\n\n[[types.type_3-1]]\nname = \"rs1_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_3-1]]\nname = \"rm\"\ntop = 2\nbot = 0\n\n[[types.type_3-1]]\nname = \"rd_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_3-1]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_3-2]]\nname = \"none\"\ntop = 31\nbot = 20\n\n[[types.type_3-2]]\nname = \"rs1_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_3-2]]\nname = \"rm\"\ntop = 2\nbot = 0\n\n[[types.type_3-2]]\nname = \"rd_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_3-2]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_3-3]]\nname = \"none\"\ntop = 31\nbot = 20\n\n[[types.type_3-3]]\nname = \"rs1_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_3-3]]\nname = \"rm\"\ntop = 2\nbot = 0\n\n[[types.type_3-3]]\nname = \"rd_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_3-3]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_4-3]]\nname = \"none\"\ntop = 31\nbot = 25\n\n[[types.type_4-3]]\nname = \"rs2_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_4-3]]\nname = \"rs1_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_4-3]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type_4-3]]\nname = \"rd_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_4-3]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_4-7]]\nname = \"none\"\ntop = 31\nbot = 25\n\n[[types.type_4-7]]\nname = \"rs2_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_4-7]]\nname = \"rs1_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_4-7]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type_4-7]]\nname = \"rd_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_4-7]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_5-2]]\nname = \"imm\"\ntop = 11\nbot = 0\n\n[[types.type_5-2]]\nname = \"rs1_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_5-2]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type_5-2]]\nname = \"rd_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_5-2]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_6-15]]\nname = \"rs3_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_6-15]]\nname = \"none\"\ntop = 26\nbot = 25\n\n[[types.type_6-15]]\nname = \"rs2_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_6-15]]\nname = \"rs1_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_6-15]]\nname = \"rm\"\ntop = 2\nbot = 0\n\n[[types.type_6-15]]\nname = \"rd_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_6-15]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[[types.type_7-1]]\nname = \"imm\"\ntop = 11\nbot = 5\n\n[[types.type_7-1]]\nname = \"rs2_Register_float\"\ntop = 4\nbot = 0\n\n[[types.type_7-1]]\nname = \"rs1_Register_int\"\ntop = 4\nbot = 0\n\n[[types.type_7-1]]\nname = \"none\"\ntop = 14\nbot = 12\n\n[[types.type_7-1]]\nname = \"imm\"\ntop = 4\nbot = 0\n\n[[types.type_7-1]]\nname = \"none\"\ntop = 6\nbot = 0\n\n[format_1-7]\ntype = \"type_1-7\"\n\n[format_2-1]\ntype = \"type_2-1\"\n\n[format_2-2]\ntype = \"type_2-2\"\n\n[format_3-1]\ntype = \"type_3-1\"\n\n[format_3-2]\ntype = \"type_3-2\"\n\n[format_3-3]\ntype = \"type_3-3\"\n\n[format_4-3]\ntype = \"type_4-3\"\n\n[format_4-7]\ntype = \"type_4-7\"\n\n[format_5-2]\ntype = \"type_5-2\"\n\n[format_6-15]\ntype = \"type_6-15\"\n\n[format_7-1]\ntype = \"type_7-1\"\n\n[mappings]\nnames = [\"Register_int\", \"Register_float\", \"Mapping_round\"]\nnumber = 32\nRegister_int = [\n    \"zero\",\n    \"ra\",\n    \"sp\",\n    \"gp\",\n    \"tp\",\n    \"t0\",\n    \"t1\",\n    \"t2\",\n    \"s0\",\n    \"s1\",\n    \"a0\",\n    \"a1\",\n    \"a2\",\n    \"a3\",\n    \"a4\",\n    \"a5\",\n    \"a6\",\n    \"a7\",\n    \"s2\",\n    \"s3\",\n    \"s4\",\n    \"s5\",\n    \"s6\",\n    \"s7\",\n    \"s8\",\n    \"s9\",\n    \"s10\",\n    \"s11\",\n    \"t3\",\n    \"t4\",\n    \"t5\",\n    \"t6\",\n]\nRegister_float = [\n    \"ft0\",\n    \"ft1\",\n    \"ft2\",\n    \"ft3\",\n    \"ft4\",\n    \"ft5\",\n    \"ft6\",\n    \"ft7\",\n    \"fs0\",\n    \"fs1\",\n    \"fa0\",\n    \"fa1\",\n    \"fa2\",\n    \"fa3\",\n    \"fa4\",\n    \"fa5\",\n    \"fa6\",\n    \"fa7\",\n    \"fs2\",\n    \"fs3\",\n    \"fs4\",\n    \"fs5\",\n    \"fs6\",\n    \"fs7\",\n    \"fs8\",\n    \"fs9\",\n    \"fs10\",\n    \"fs11\",\n    \"ft8\",\n    \"ft9\",\n    \"ft10\",\n    \"ft11\",\n]\nMapping_round = [\"rne\", \"rtz\", \"rdn\", \"rup\", \"rmm\", \"unknown\", \"unknown\", \"dyn\"]\n\n[format_1-7.repr]\ndefault = \"$name$ %rd_Register_float%, %rs1_Register_float%, %rs2_Register_float%, %rm%\"\n\n[format_2-1.repr]\ndefault = \"$name$ %rd_Register_int%, %rs1_Register_float%\"\n\n[format_2-2.repr]\ndefault = \"$name$ %rd_Register_float%, %rs1_Register_int%\"\n\n[format_3-1.repr]\ndefault = \"$name$ %rd_Register_int%, %rs1_Register_float%, %rm%\"\n\n[format_3-2.repr]\ndefault = \"$name$ %rd_Register_float%, %rs1_Register_int%, %rm%\"\n\n[format_3-3.repr]\ndefault = \"$name$ %rd_Register_float%, %rs1_Register_float%, %rm%\"\n\n[format_4-3.repr]\ndefault = \"$name$ %rd_Register_int%, %rs1_Register_float%, %rs2_Register_float%\"\n\n[format_4-7.repr]\ndefault = \"$name$ %rd_Register_float%, %rs1_Register_float%, %rs2_Register_float%\"\n\n[format_5-2.repr]\ndefault = \"$name$ %rd_Register_float%, %imm%(%rs1_Register_int%)\"\n\n[format_6-15.repr]\ndefault = \"$name$ %rd_Register_float%, %rs1_Register_float%, %rs2_Register_float%, %rs3_Register_float%, %rm%\"\n\n[format_7-1.repr]\ndefault = \"$name$ %rs2_Register_float%, %imm%(%rs1_Register_int%)\"\n\n[format_1-7.instructions.\"fadd.s\"]\nmask = 0xfe00007f\nmatch = 0x53\n\n[format_1-7.instructions.\"fdiv.s\"]\nmask = 0xfe00007f\nmatch = 0x18000053\n\n[format_1-7.instructions.\"fmul.s\"]\nmask = 0xfe00007f\nmatch = 0x10000053\n\n[format_1-7.instructions.\"fsub.s\"]\nmask = 0xfe00007f\nmatch = 0x8000053\n\n[format_2-1.instructions.\"fclass.s\"]\nmask = 0xfff0707f\nmatch = 0xe0001053\n\n[format_2-1.instructions.\"fmv.x.w\"]\nmask = 0xfff0707f\nmatch = 0xe0000053\n\n[format_2-2.instructions.\"fmv.w.x\"]\nmask = 0xfff0707f\nmatch = 0xf0000053\n\n[format_3-1.instructions.\"fcvt.w.s\"]\nmask = 0xfff0007f\nmatch = 0xc0000053\n\n[format_3-1.instructions.\"fcvt.wu.s\"]\nmask = 0xfff0007f\nmatch = 0xc0100053\n\n[format_3-2.instructions.\"fcvt.s.w\"]\nmask = 0xfff0007f\nmatch = 0xd0000053\n\n[format_3-2.instructions.\"fcvt.s.wu\"]\nmask = 0xfff0007f\nmatch = 0xd0100053\n\n[format_3-3.instructions.\"fsqrt.s\"]\nmask = 0xfff0007f\nmatch = 0x58000053\n\n[format_4-3.instructions.\"feq.s\"]\nmask = 0xfe00707f\nmatch = 0xa0002053\n\n[format_4-3.instructions.\"fle.s\"]\nmask = 0xfe00707f\nmatch = 0xa0000053\n\n[format_4-3.instructions.\"flt.s\"]\nmask = 0xfe00707f\nmatch = 0xa0001053\n\n[format_4-7.instructions.\"fmax.s\"]\nmask = 0xfe00707f\nmatch = 0x28001053\n\n[format_4-7.instructions.\"fmin.s\"]\nmask = 0xfe00707f\nmatch = 0x28000053\n\n[format_4-7.instructions.\"fsgnj.s\"]\nmask = 0xfe00707f\nmatch = 0x20000053\n\n[format_4-7.instructions.\"fsgnjn.s\"]\nmask = 0xfe00707f\nmatch = 0x20001053\n\n[format_4-7.instructions.\"fsgnjx.s\"]\nmask = 0xfe00707f\nmatch = 0x20002053\n\n[format_5-2.instructions.flw]\nmask = 0x707f\nmatch = 0x2007\n\n[format_6-15.instructions.\"fmadd.s\"]\nmask = 0x600007f\nmatch = 0x43\n\n[format_6-15.instructions.\"fmsub.s\"]\nmask = 0x600007f\nmatch = 0x47\n\n[format_6-15.instructions.\"fnmadd.s\"]\nmask = 0x600007f\nmatch = 0x4f\n\n[format_6-15.instructions.\"fnmsub.s\"]\nmask = 0x600007f\nmatch = 0x4b\n\n[format_7-1.instructions.fsw]\nmask = 0x707f\nmatch = 0x2027\n";